1. Field of the Invention
The present invention relates to an improved semiconductor read-only memory (referred to hereinafter as a PROM) having a diode which is written into by shorting its junction. More particularly, the present invention relates to a structure of a memory cell which achieves increased integration density and increased operation speed.
2. Description of the Related Art
The principle of a typical junction shorting PROM is illustrated in FIG. 1. The PROM includes word lines W.sub.o, W.sub.1, . . . , bit lines B.sub.o, B.sub.1, . . . , and memory cells, respectively connected at intersections of the word lines and bit lines. A memory cell MC includes a series connection of a transistor Q and a diode D which is polarized so as to block a current flowing through the transistor. The cathode of the diode is connected to a bit line, and the base of the transistor is connected to a word line. The structure of the memory cell is shown in the cross-sectional view of FIG. 1(b). A n.sup.+ -type region 1 and a p.sup.+ -type region 2, beneath the n.sup.+ -type region 1, form the cathode and the anode of the diode D, respectively. The p.sup.+ -type region 2, a n-type region 3 and a substrate SUB form an emitter, base and collector of a pnp transistor Q, respectively. The pn junction of the diode is shorted by applying a voltage higher than the breakdown voltage of the reverse connected diode D. That is, a current high enough to short the pn junction of the diode is applied during a write-in operation. A shorted memory cell is indicated by MC' in FIG. 1(b). When a word line having a shorted diode connected thereto is selected (i.e., addressed) by applying a low level "L" to the base of the transistor Q, the transistor becomes conductive and pulls the connected bit line down to the low level "L". However, when the diode is not written into, the diode is non-conductive and the connected bit line is not pulled down, keeping the high level "H" on the selected bit line connected to this memory cell, even if the transistor Q becomes conductive. Thus, an addressed bit line having the high level "H", can read out "1" or "0" data stored in the memory cell connected thereto, by detecting whether a current flows into the bit line.
Since PROMs, having 256 and 512 bits, were first developed in 1970, their memory capacity has been enhanced to 64K bits. Further increase in the integration capacity is still expected. Reviewing the history of the development of PROMs, at early stages of junction-shorting type PROMs, a gold diffused TTL technique was employed. Thereafter, a more precise lithography technique for greater density integration, a washed emitter technique, and a mask self-alignment technique have been employed. In addition to these techniques, a technique for suppressing a parasitic thyristor effect caused by the increased integration density has been developed. These are reported by the present inventors in "An Advanced SVG Technology for 64K Junction-Shorting PROM's", IEEE Transactions on Electron Devices, Vol. ED-30, No. 12, December, 1983. The problems of the thyristor effect shall be further described in some detail.
When one of the memory cells is written into and an adajcent memory cell, fabricated on a common epitaxial layer, is not written into, a parasitic pnpn element is provided. That is, a thyristor is produced between these two cells, as shown by the dotted lines in FIG. 1(c). If the thyristor turns on, the selected bit line B.sub.1 having a high level "H" is clamped to the unselected bit line B.sub.o having a low level "L". In this state, any other memory cell connected to the bit line B.sub.1 cannot be written into because there is insufficient voltage on the bit line B.sub.1. As is widely known, a thyristor is composed of two transistors, a npn transistor and a pnp transistor, and the breakdown voltage V.sub.Bo of the thyristor is determined using the following formula: EQU V.sub.Bo =V.sub.CBo (1-a.sub.n -a.sub.p).sup.1/n ( 1)
and the thyristor latches at: EQU a.sub.n +a.sub.p .congruent.1 (2)
where V.sub.CBo denotes the collector-base breakdown voltage of the parasitic npn transistor, a.sub.n and a.sub.p denote the current amplification factors of the npn transistor and the pnp transistor, respectively, and n is a constant.
Consequently, in order to prevent the latching of the thyristor, V.sub.Bo must be large, that is, the current amplification factors a.sub.n and a.sub.p should be small. For this purpose, the p.sup.+ -type layer, i.e., the base B of the parasitic npn transistor, is thick as shown in FIG. 1(d), resulting in a reduced current amplification factor a.sub.n. Furthermore, this thick region also raises the breakdown voltage of the transistor Q. Another measure for preventing the latching of the thyristor includes staggering adjacent memory cells so as to reduce face-to-face portion the peripheral length of the emitters. This results in lowered current amplification factors of the parasitic transistors. These techniques contribute to increasing integration density to produce PROMs of 8K to 256K bits. In addition, the size of the memory cell has shrunk from 1820 .mu.m.sup.2 to 1260 .beta.m.sup.2.
However, as long as a gold diffused TTL process is employed, the following problems still remain unsolved for the following reasons. First, because of a segregation problem of gold, a thick epitaxial layer is required (approximately 7 .mu.m) and consequently, the deeply diffused p.sup.+ -type base layer (approximately 2 .mu.m) causes a wider lateral diffusion, resulting in a wider surface occupation area. This limits the integration density. Second, control of gold-doping is difficult because the larger the wafer size becomes, the more uncontrollable the heat capacity becomes. Therefore, the diameter of the wafer cannot be increased. Third, gold particles in the diffused layer cause emitter and collector junctions to short. Therefore, the base width of transistors cannot be reduced and an increase in the current amplification factors of the transistors is limited (i.e., the h.sub.FE is approximately 25 to 100). Thus, there are limitations on the reduction in power consumption of the circuit as well as on increasing the operation speed. Fourth, the logic circuit must be saturated, and therefore, the switching speed is limited and cannot be increased.
In order to solve the above-mentioned problems, V-shaped isolation grooves, or so-called SVG (shallow V-shaped grooves), provide perfect separation of the elements by a relatively shallow groove, as shown by V.sub.1 in FIG. 1(f). The V-shaped grooves extend into the upper portion of the buried n.sup.+ -type layer BL, i.e., a buried base lead, from the surface of the epitaxial layer, and perfectly isolate the epitaxial layer of each memory cell. Some conduction may exist through the buried n.sup.+ -type layer B, however, the minority carriers in the epitaxial region cannot diffuse into an adjacent cell because the n.sup.+ -type layer BL is highly doped and recombination of the carriers occurs therein. V.sub.2 indicates another isolation groove which extends into the substrate SUB and completely isolates each memory cell block.
Introduction of the SVG technique allows a process other than gold diffusion to be employed, and thus, advantages are achieved. The advantages include that the parasitic thyristor effect between adjacent cells is completely eliminated. A thin epitaxial layer (having a thickness of approximately 3 .mu.m) as well as a thin p.sup.+ -type diffused base layer (having a thickness of approximately 0.7 .mu.m) can be employed in npn transistors of the peripheral circuits, and the integration density can be increased. A wafer diameter can be increased, therefore increasing production efficiency. In addition, the base width of the npn transistor of the peripheral circuit is thin so that the current amplification factor of the transistor is large (i.e., the h.sub.FE is approximately 70 to 250), resulting in a high speed operation as well as lower power consumption in the peripheral circuits. In addition, the Schottky diode-clamped TTL technique is employed in peripheral circuits to increase the operation speed.
As described above, due to the V-shaped groove, a 256 to 64K bit PROM employing Schottky diode clamped TTL can be obtained. The area of the memory cell is reduced from 864 .mu.m.sup.2 to 252 .mu.m.sup.2. This art is reported by the present inventors in "A 40 ns 64K bit Junction-Shorting PROM", IEEE Journal of Solid State Circuits, Vol. SC-19, No. 2, April 1984. However, problems still remain which will be described hereinafter.
SVG isolation is performed by widely known anisotropic etching which uses the characteristics of the (100) crystal orientation of silicon. As is widely known, the relation between the width W of the mask and the depth D of the groove is given by the formula: EQU D=(1/2)W tan54.degree..gtoreq.0.7W (3)
Therefore, when the epitaxial layer is 3 .mu.m thick and the upward diffusion region of the n.sup.+ -type buried layer is 1 .mu.m thick, the width of the SVG is 3 .mu.m (a difference of 2 .mu.m is required). This is automatically determined. Therefore, additional reduction in the isolation width is not possible.
Furthermore, as is widely known, in V-shaped isolation grooves, portions of silicon dioxide (approximately 1 .mu.m on each side of the V-shaped groove) expand laterally along the surface and form a birds-beak. Therefore, a margin area between adjacent patterns is required, and integration density cannot be improved.
The isolation effect of the SVG occurs when the groove extends into the n.sup.+ -type buried layer. Thus, a thin epitaxial layer is required if the groove width at the surface is to be narrow. Therefore, upward diffusion of the n.sup.+ -type buried layer must be sufficiently controlled. This, however, is difficult. On the other hand, in order to maintain the reliability of the write-in operation, the depth of the p.sup.+ -type layer, i.e., the emitter of the pnp transistor Q, is generally required to be approximately 1.2 .mu.m thick. In order to obtain a voltage of more than 20V (which is larger than the breakdown voltage between the base and the emitter during a write-in operation), the width of the depletion layer is generally required to be approximately 1 .mu.m. Therefore, if the upward diffusion of the buried layer is 1 .mu.m, the epitaxial layer is required to be at least 3 .mu.m thick.
Further increases in the operation speed and integration density, and/or decreases in the power consideration in the peripheral circuit, which includes, for example, X and Y address inverters, decoder/drivers and a multiplexer, and is connected to receive a chip-enable signal, must be achieved. For solving these problems, stray capacitance in the circuits, particularly the stray capacitance of the word lines, must be reduced and performance of the transistors in the circuits must be up-graded in order to ease the current load of the circuits. An explanation regarding the relationship between these factors and their effects shall be provided in view of the preferred embodiments described in detail herein below.